This invention relates to a nonvolatile semiconductor storage device such as an EEPROM (Electrically Erasable and Programmable ROM), and more particularly to a device for storing information using a residual dielectric polarization of a ferroelectric substance.
As a conventional nonvolatile semiconductor storage device of this kind, known are devices such as shown in FIGS. 5 and 6.
The nonvolatile semiconductor storage device shown in FIG. 5 comprises memory cells each of which consists of one memory transistor MTr and two select transistors STr1 and STr2. The memory transistor MTr is a field-effect transistor having a gate structure in which a metal film, a ferroelectric substance film and a semiconductor film are laminated from the top in this sequence.
Hereinafter, the operations of writing, erasing and reading data for a memory cell C1 will be briefly described.
When a data is to be written into the cell, word lines WL1.sub.1 and WL1.sub.2 are grounded and a positive voltage (e.g., 5 V) is applied to a word line WL1.sub.3. Under this state, a positive high voltage (e.g., 10 V) is applied to a bit line BL1, so that the ferroelectric substance film of the memory transistor MTr is affected by an electric field through the select transistor STr2 of the memory cell C1, whereby the ferroelectric substance film is polarized. This causes the memory transistor MTr which is an N-channel transistor, to become a nonconductive state. This state is defined as the write state in which data "1" is written in the memory cell.
When the written data is to be erased, the word lines WL1.sub.1 and WL1.sub.3 and the bit line BL1 are grounded and a positive high voltage is applied to the word line WL1.sub.2. This causes the ferroelectric substance film of the memory transistor MTr of the memory cell C1 to be affected by an electric field which is opposite in direction to that in the writing process, so that the ferroelectric substance film is polarized to the reverse polarity. As a result, the N-channel memory transistor MTr becomes a conductive state (namely, the state in which data "0" is stored).
When a data is to be read, a positive voltage is applied to the word lines WL1.sub.1 and WL1.sub.3 and the word line WL1.sub.2 is grounded. A sense amplifier SA connected to the bit line BL1 detects the flow of a current. When no current flow is detected, it means the reading of data "1", and, when a current flow is detected, it means the reading of data "0".
In contrast, the nonvolatile semiconductor storage device shown in FIG. 6 comprises memory cells each of which consists of one select transistor STr and one ferroelectric capacitor FC.
The process of writing a data into a memory cell C1 is performed by applying a positive voltage to a word line WL1 and a positive high voltage to a bit line BL1, thereby making the ferroelectric capacitor FC a certain polarization state.
The data erasing process is performed by applying a positive voltage to the word line WL1 and a negative high voltage to the bit line BL1, thereby polarizing the ferroelectric capacitor FC to the reverse polarity.
In the data reading process, a positive voltage is applied to the word line WL1 and a positive voltage is applied to the bit line BL1, and the contents of the written data, i.e., "1" or "0" is judged depending on the level of a current detected by a sense amplifier SA which is connected to the bit line BL1.
The thus configured prior art examples have the following problems.
The nonvolatile semiconductor storage device shown in FIG. 5 has a problem in that the configuration where one memory cell consists of one memory transistor and two select transistors causes the cell size to become large, and therefore this configuration is not adequate for a high integration.
The nonvolatile semiconductor storage device shown in FIG. 6 has a configuration which may be subjected to an integration of a certain degree. In such a storage device, however, a so-called destructive readout in which the polarization state of the ferroelectric capacitor is changed by a current flowing into the capacitor during the data reading process is conducted, so that the refresh operation is required to be performed for retaining the written data. As a result, there arises a problem in that the periphery circuitry has a complex configuration.